搜索资源列表
Principles-of-Verifiable-RTL-Design
- 本书主要以HDL（verilog/vhdl）为例，详细讲述了在IC DESIGN FLOW中 Verification 以及Test的设计思想、方法和技巧，涵概了测试的各个方面， 是目前进行IC设计的同仁们最为推荐的一本宝典-(Kluwer) Principles of Verifiable RTL Design (2nd Ed.)
RTL
- Booth radix2 MAC UNIT In verilog
华为verilog编程规范
- 华为verilog编程规范，本规范规定了Proverilog编码规范，即采用verilog代码设计时的代码书写规范。本规范适用于逻辑芯片开发中使用verilog语言作为RTL级设计语言。
rtl
- 通过verilog实现pc串口和fpga的双向通信。代码是老外写的，非常严谨-the verilog code comnunicate with the pc by serial port
rtl_wangjiangxing
- ecc椭圆算法RTL,verilog经过验证-ecc verilog
RTL
- HMI产品上使用的将黑白屏提升分辨率变为彩色屏的verilog RTL code-verilog RTL code for convert Black/White HMI to high resolution color
rs_decoder_31_19_6.tar
- RS Decoder RTL verilog Code
lcd1.tar
- LCD Control RTL Verilog Code
spimaster.tar
- SPI Interface Master Control RTL Verilog Code
spi_boot-rel_3_1_rev_C.tar
- SPI Boot Interface Control RTL Verilog Code
rtl
- SPI verilog RTL code
rsencoder.tar
- RS Encoder RTL verilog Code
ultimate_crc.tar
- Ultimate CRC Check RTL Verilog Code
i2c_master
- verilog i2c master rtl+testbench 转自特权同学(verilog i2c master rtl+testbench)
i2c_slave
- Verilog i2c slave rtl + testbench 仿真ok(Verilog i2c slave rtl + testbench)
BCH_VLSI
- 使用HLS完成BCH编码的运算通路的设计，纯组合逻辑，对于65nm工艺可跑上1GHz。已经组合逻辑分为了多个部分，可在每一个部分之间插流水线。 附上可综合的纯RTL Code以及C++代码，以及Modelsim仿真。 可通过我的优化选项来学习如何优化HLS工具生产的代码。(BCH Encoder realized using HLS tool. Combinational logic.)
eetop.cn_simple_spi
- spi 模块代码 RTL verilog(spi rtl code)
rtl
- 基于S10新品的2x2矩阵乘模块，附带双精度的乘法，除法ip核(2x2 matrix multiplication module based on S10 new product, with double precision multiplication, division IP kernel)
8051
- The resource code of The 8051 microcontroller is member of MCS-51 family, originally designed in the 1980's by Intel. The 8051 has gained great popularity since its introduction and is estimated it is used in a large percentage of all embedded system
rtl
- 实现AD7606数据采集，基于xilinx的6系列(Realization of AD7606 data acquisition)